In previous architectures, MIG provided Address/Control, Write, and Read timing spreadsheet (timing budgets) in the associated application notesand the "doc" directory in a generated core.For the Virtex-6 and Spartan-6 FPGA designs, timing budgets are not provided.
Is there a plan to release these budgets, and if not, why?
There are noplans to release timing budgets for Virtex-6 and Spartan-6 FPGA designs as was done in previous architectures.
For Virtex-6 FPGA, due to the complexity of the design, it is very difficult to model the design through a timing budget to accurately reflect the achievable performance. Characterization is the absolute best way to provide and guarantee performance.
For Spartan-6 FPGA, the goal of the MIG is to provide a simple, easy to use, drop-in memory solution.With this strategy, Xilinx made simplifying assumptions to make the MIG easier to use, such as the assumption that there is no skew between MIG outputs on the same clock domain. In addition, the Spartan-6 MCB has been extensively characterized (over full process, voltage and temperature) following the board layout guidelines mentioned in the Spartan-6 FPGA Memory Controller User Guide(UG388).The internal characterization Xilinx performed should be used as a guarantee of the specified performance rather than a timing budget.