If you are presenting your TLPs at the user interface perfectly aligned to the trn_clk or user_clk_out (AXI), then you may experience issues. Please make sure to slightly delay your data relative to the clock. Otherwise, the simulation may fail with otherwise unexplained issues.
For Verilog do something like this:
assign #1 new_signal = old_signal;
always @(posedge user_clk_out)
begin
new_signal = #1 old_signal;
end
For VHDL:
new_signal <= old_signal after 1 ps;
process (user_clk)
begin
if (user_clk'event and user_clk = '1') then
new_signal <= old_signal after 1 ps;
end process;
Revision History:
10/11/2010 - Initial Release