We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 37757

LogiCORE Video On Screen Display (OSD) v1.0 - How long do I need to assert hblank and vblank?


How long do I need to assert hblank and vblank?



The minimum requirement for hblank is based on the number of channels. If you are using two channels, they must assert hblank for two clock cycles, and if they are using three channels, then hblank must be asserted for three clock cycles.


The minimum requirement for vblank is based on the use of the graphics controller. If you are using the graphics controller of the On Screen Display (OSD), then the vblank must be held for one line. If you are not using the graphics controller, then the vblank can be as short as one clock cycle. This one cycle can be pulsed before an hblank.

For a detailed list of LogiCORE IP Video On Screen Display Release Notes and Known Issues, see (Xilinx Answer 33257).
AR# 37757
Date 08/30/2010
Status Active
Type General Article
  • On-Screen Display
Page Bookmarked