Work-around:
All the GTH transceivers utilized in AC-JTAG testing must be instantiated and initialized in an FPGA design before starting the AC-JTAG test. The recommended procedure is as follows:
1. Configure the FPGA with a design in which all of the following are implemented within the FPGA design:
a. All the utilized GTH transceivers are instantiated.
b. All the utilized GTH transceivers are initialized. For proper initialization of the GTH:
i. The reference clock of the correct frequency must be provided
ii. The DCLK must be provided
iii. The initialization sequence must be performed as specified in
(Xilinx Answer 37412).
2.Wait for the configured FPGA to complete its GTH initialization sequence.The GTH initialization sequence is indicated by the internal GTH Quad Port GTHINITDONE signal. One solution for ensuring the GTH initialization sequence is complete is for the FPGA design to route the GTHINITDONE signal to a pin that the boundary-scan test tool can sample after the completion of the FPGA configuration procedure. An alternate solution is to wait after the completion of the FPGA configuration procedure for a minimum time. For example, a wait counter of 256,000 TCK cycles can be used as the wait time before starting the AC-JTAG test. The recommendation of 256,000 cycles assumes that the FPGA design is implemented with an internal DCLK of 50 MHz and that the TCK clock of 50 MHzis used.
3. Perform the AC-JTAG test
Additional requirements of the work-around:
Because the FPGA is configured for the boundary-scan test, the Xilinx BSDLanno tool must be used to generate a BSDL file that matches the FPGA configuration. See the Xilinx Command-Line Tools manual for operation of BSDLanno:
http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_2/devref.pdf