Add the following constraints to the UCF file:
PIN "core/pcie_clocking_i/GEN2_LINK.pipe_clk_bufgmux.CE0" TIG;
PIN "core/pcie_clocking_i/GEN2_LINK.pipe_clk_bufgmux.CE1" TIG;
Also, enabling pipeline registers on the read and write side of the Transaction Block RAM can help. To perform this, on page 10 of the CORE Generator Customization GUI, select the option for "Buffer Write and Read".
Pipeline Registers for Transaction Block RAM Buffers = Buffer Write and Read
Revision History
01/18/2012 - Updated; added reference to 45723
07/06/2011 - Updated for v2.4 and ISE 13.2 software release
02/03/2011 - Updated for v2.3 and v1.7 release
12/24/2010 - Updated for v2.2 release
10/11/2010 - Added constraint for CE0 pin
10/05/2010 - Updated for v1.6 release
09/02/2010 - Added note about pipeline registers
08/31/2010 - Initial Release
NOTE: "Version Found" refers to the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 45723 | Virtex-6 FPGA Integrated Block for PCI Express - Release Notes and Known Issues for all AXI Interface Versions | N/A | N/A |
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 40446 | Virtex-6 FPGA Integrated Block Wrapper v1.7 for PCI Express - Release Notes and Known Issues | N/A | N/A |
| 39353 | Virtex-6 FPGA Integrated Block Wrapper for PCI Express - Resolved issues in v2.2 | N/A | N/A |
| 37937 | Virtex-6 FPGA Integrated Block Wrapper for PCI Express - Resolved issues in v2.1 | N/A | N/A |
| 37936 | Virtex-6 FPGA Integrated Block Wrapper v1.6 for PCI Express - Release Notes and Known Issues | N/A | N/A |