We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Page Bookmarked

AR# 378

XACT 5: Using ViewSim to simulate board-level epld design


The method for preparing a board level simulation netlist for XEPLDs using
the XACT 5 software is as follows:

1. Make sure all symbols in the EPLD design schematic(s) are from the
xc7000 library; the xc7000 alias allows you to mix technologies
in the board level simulation.

2. Generate symbol(s) for the EPLD design(s). You can run each design
through XEMAKE to generate a <design>.XSF file, then use symgen -v
to automatically generate a chip symbol.

3. To generate the system functional model, just run VSM (you don't need
to run WIR2XNF).

4. When you simulate, remember to pulse the PRLD global signal high at
the beginning to initialize the registers in the XEPLD(s). PRLD is not a
pin on the XEPLD chip symbol.

For timing simulation, run each EPLD design through the fitter separately.
Instead of running Xsimmake as usual to generate VSM files, generate
WIR files manually as follows:

1. For each XEPLD design, run VMH2XNF then run xnf2wir with the -l
option to tag each symbol with the xc7000 alias.

2. Run vsm on the system design. The wirelist file found for each XEPLD
symbol will be the timing model created by xnf2wir. Note that many of
the internal nodes will no longer be visible due to fitter optimization
(XEPLDs do not yet support XNF file back-annotation, as is done for
FPGAs using the XNFBA program).


AR# 378
Date 03/20/2000
Status Archive
Type General Article