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AR# 37817 Design Assistant for PCI Express - How does a Gen 1 endpoint handle the reserved bits in the TS1/TS2 ordered sets that are used in Gen 2?

Description

For Gen 1 PCIe, bit 0 and bits 2:7 of the TS1/TS2 ordered sets were reserved and set to 0. However, these bits are used for Gen 2 PCIe. Do Xilinx cores correctly interpret these bits if in Gen 1 or Gen 2 mode?

NOTE: This Answer Record is part of the Xilinx Solution Center for PCI Express(Xilinx Answer 34536). TheXilinx Solution Center for PCI Express is available to address all questions related to PCIe. Whether you are starting a new design with PCIe or troubleshooting a problem, use the Solution Center for PCIeto guide you to the right information.

Solution

A Gen 1 endpoint such as the Spartan-6 endpoint or Virtex-6 endpoint operating in Gen 1 mode transmits 0b for these bits as required by the specification. If the Gen 1 endpoint is interfacing with a Gen 2 capable device that is transmitting non-zero values for these bits, the Xilinx Gen 1 endpoint correctly ignores these settings.

Revision History
10/06/2010 - Initial Release

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
36062 Design Assistant for PCI Express - Start here with questions about core functionality or protocol N/A N/A
34538 Xilinx Solution Center for PCI Express - Design Assistant N/A N/A

Actions

AR# 37817
Date Created 10/08/2010
Last Updated 12/15/2012
Status Active
Type General Article
IP
  • Spartan-6 FPGA Integrated Endpoint Block for PCI Express ( PCIe )
  • Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )
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