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AR# 37856

12.3 EDK - How do I use EDK AXI IP cores in a system with no processor?

Description

This Answer Record demonstrates how to use EDK IP in ISE Project Navigator without necessarily using a processor.

The example task is to create a Virtex-6 DDR3 memory controller with 2 master AXI4 ports without a microprocessor.A similar process can be followed to utilize other EDK IP. EDK XPS is used to create, connect, deliver, and update the IP cores as an EDK subsystem.

Embedded processing experience is not needed for this flow. The completed ISE and EDK XPS project is available from: http://www.xilinx.com/txpatches/pub/applications/misc/ar37856.zip

Solution

Launching XPS from Project Navigator

Start with an ISE Project Navigator existing Virtex-6 FPGA project open.

To start an EDK subsystem, select the menu Project-> New Source, and choose "Embedded Processor". Type a subsystem name of system, or other label. Thisis the component name that is to be instantiated outside of XPS.

New Source Wizard
New Source Wizard


Agree with Yes to create a Base System using the BSB Wizard.

BSB?

Base System Builder
The EDK Base System Builder (BSB) wizard is used for this example as it creates an complete EDK system. For this answer records purposes, it connects the somewhat complex clocking structure of the DDR3 SDRAM controller. The BSB design hascores that are not needed, like a MicroBlaze processor, thatis later manually removed. When more experienced, starting from a blank project for simple IP cores can be used instead of BSB.

Choose to create an AXI design:

Choose AXI
Choose AXI


Select I would like to create a new design
At the Board Selection page, choose any desired settings. In this case a custom board is chosen with an active-high reset.

Board Selection
Board Selection


At the System Configuration page, choose a single processor:

System Configuration
System Configuration


At the Processor Configuration page, choose a Reference Clock Frequency that matches the main clock input that the EDK peripherals use, if known. Other settings can be ignored.

Processor Configuration
Processor Configuration


At the Peripheral Configuration page, click Add Device... and add any peripherals that are desired and also available in this list. Additional peripherals not seen here will be available after completing the BSB wizard. For this example, only a DDR3_Memory and a UART is chosen. The UART is chosen from I/O Devices.

DDR3_MEMORY
DDR3_MEMORY


Click next through the Cache Configuration page, and choose Finish to complete the BSB wizard.

Choose to Start Using Platform Studio.The XPS GUI opens with a complete EDK system.
Initial EDK Subsystem
Initial EDK Subsystem


Delete Unneeded Peripherals
In the Bus Interfaces tab, ctrl-click all undesired processor and utility cores, and right-click Delete Instances.... In this case, all coresare removed except for the memory controller, the non-lite interconnect, the clock generator, and reset cores.

Deleting Unneeded Peripherals
Deleting Unneeded Peripherals


Then Delete selected instances and all their connections. This removes the external ports and internal nets used by the unneeded cores.

Delete All Connections
Delete All Connections


Adding External AXI Interfaces
In this example, two external master AXI ports are to be connected to the memory controller through the interconnect. The memory controller and any I/O peripherals selected in BSB are already connected to the outside system.For the two user AXI master connections to DDR3 memory, two AXI External Master Connectorsareparameterized, connected to the AXI Interconnect, and finally exposed externally.

From the IP Catalog tab, choose AXI External Master Connector and right-click Add IP...

Add IP: External Master
Add IP: External Master


The connector core configuration window opens. Settings in this GUI actually configure the AXI Interconnect settings for this interface. Click the PDF symbol in the upper-right corner to open the data sheet for more detailed parameter documentation.

The User and System tabs should reflect the functional properties of the external user logic. No changes are required for this example.

Connector User Tab
Connector User Tab


Connector System Tab
Connector System Tab


The Interconnect Settings for BUSIF tab parameterizes the port of the AXI Interconnect this connectoris tobe interfacing to. Register pipelining, clock conversion, and FIFOs in the interconnect can be enabled. However, no changes are required for this example.

Connector Interconnect Settings
Connector Interconnect Settings


Click OK to exit the connector settings GUI back to XPS.

Connecting External Master to AXI Interconnect
In the Bus Interfaces tab, connect the master connector M_AXI interface to the DDR3 S_AXI slave interface by clicking their open master (square) and slave (circle) interface connections in a vertical alignment. This connects nearly all individual AXI signals from the connector to the interconnect, and creates an access path from the connector to the DDR3 controller.

Connect Connector_0 to Interconnect
Connect Connector_0 to Interconnect


Connecting Signals and External Ports
Since the AXI Interconnect can perform clock synchronization, the connector clock may not be connected by default. Connect a clock in the Ports tab by expanding the (BUS_IF) M_AXI net bundle and choosing a clock- in this case, an existing 100MHz clock net.

Connect AXI Clock
Connect AXI Clock


Externalizing AXI Signals from XPS
To make the connector AXI I/O signals available outside of the EDK subsystem, select the Make Ports External of the (IO_IF) external_axi_if net bundle. This connects an entire set of individual AXI signals externally.

Make Ports External
Make Ports External



Verify the connections exist by expanding the External Ports tab.The net names on the left appear in the component instantiation generated later in Project Navigator.

Any individual signals can be connected and brought external to the EDK system in the same manner as the previous two steps. For example, if the clock generator and/or reset blocks were removed earlier, clock and reset ports of various IP would be connected in this Ports tab. For this example, the first connector is now complete.

Repeat for Second External Connector

Repeat the process for the second master connector. Add the connector IP core, parameterize, connect to AXI Interconnect, connect a clock, and Make Ports External:

Second Connector Interfaces
Second Connector Interfaces


Second Connector I/O
Second Connector I/O


DDR3 Memory Controller

Before completing this particular example, the DDR3 Memory Controller must also be configured.

In the Addresses tab, choose the Base Address of the memory controller slave interface to be set to 0x0. This conveniently allows the external AXI addressesto start at address 0 instead of the arbitrary base address that was chosen by BSB.A more complex EDK subsystem with multiple slaves needing different addresses would be configured here.
DDR3 Base Address
DDR3 Base Address


The axi_v6_ddrx memory controller is nearly identical to the Coregen MIG controller. In a similar manner to MIG, the axi_v6_ddrx controller must be configured and an I/O pinout chosen. EDK then internally manages the generated UCF, so no I/O constraints are necessary in Project Navigator. To launch the axi_v6_ddrx MIG GUI, from the Bus Interfaces tab, right-click the DDR3 Memory core and choose Configure IP.

DDR3 Configure IP...
DDR3 Configure IP...


Continue through the memory GUI, for this example generally keeping the defaults. Note that the AXI Parameter Options page contains similar settings as the AXI Master Connector configuration. In the same manner, they configure the AXI Interconnect interface the memory is connected to.

If necessary to continue, deselect the Use EDK calculated clock period checkbox, and enter a period of 2500 ps. Complete the DDR3 GUI with Finish.

DDR3 Clock Frequency
DDR3 Clock Frequency


Design Check
To make sure the system has been correctly configured, run the Hardware -> Generate Netlist process from the menu.

Generate Netlist
Generate Netlist


This performs a series of system and core-level DRCs and synthesize the entire EDK subsystem. Any errors should be corrected. Finally, close XPS.

Project Navigator Final Integration
In ISE Project Navigator, Select the XPS system.xmp source and run the View HDL Instantiation Template.

Instantiation Template
Instantiation Template


Using the template, instantiate the EDK instance into any user HDL code.


Upgrading the EDK Subsystem


One of the benefits of XPS managing the subsystem is to take advantage of EDK revup capabilities.After installing a new Xilinx IDS tool version, double-click the XPS system to launch XPS.The EDK upgrade wizard should launch. Note that any major version upgrades must be manually updated to be used.


Next Steps: How to Create Custom AXI IP

(Xilinx Answer 37425) - 12.3 EDK, 12.3 ISE - How do I create a custom AXI IP core?

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
43822 14.x CoreGen - AXI Interconnect - Does the AXI Interconnect support multiple Masters? N/A N/A
AR# 37856
Date Created 10/04/2010
Last Updated 12/15/2012
Status Active
Type General Article
Tools
  • EDK - 12.3
  • EDK - 13.1