We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 37860

VCS - Warning-[PISB] Parameter in specify block RAMB18E1.v ... Parameter 'RAM_​MODE' is used in a specify block.


When I compile my design which makes use of the RAMB18E1 hard block in a Virtex-6 device, there are several warnings similar to the following:
Warning-[PISB] Parameter in specify block RAMB18E1.v, 584
Parameter 'RAM_MODE' is used in a specify block.

Why do these warnings occur and how can I resolve the issue?


VCS strictly adheres to the Verilog LRM which states that parameters cannot be used within specify blocks. However, this issue does not affect the behavior of the model and can be ignored.
This issue is currently under investigation and is to be addressed it in a future release of the ISE design tools.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
58891 Xilinx Simulation Solution Center - Design Assistant - Third Party Simulators - Synopsys VCS​/VCS-MX N/A N/A
AR# 37860
Date Created 09/16/2010
Last Updated 05/26/2014
Status Archive
Type General Article
  • ISE - 10.1
  • ISE Design Suite - 11.1
  • ISE Design Suite - 11.2
  • More
  • ISE Design Suite - 11.3
  • ISE Design Suite - 11.4
  • ISE Design Suite - 11.5
  • ISE Design Suite - 12.1
  • ISE Design Suite - 12.2
  • Less