UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 37861

MIG v3.6-v3.61 Virtex-6 DDR3 - Multi-Controller VHDL designs can exhibit data errors in simulation when targeting an RDIMM

Description

MIG v3.6-v3.61 Multi-controller DDR3 SDRAM VHDL designs are exhibiting data errors in certain configurations if one of the controllers targets an RDIMM.

These data errors have been observed in configurations with smaller CAS Latency/lower frequency.

This issue is occurring due to incorrect construction of an if-else statement in the sim_tb_top module.

This issue does not exist for any Verilog designs, single controller VHDL designs, or multi-controller VHDL designs that do not target an RDIMM.

Solution


The incorrect if-else structure exists in specific pipelining logic within the sim_tb_top.vhd testbench module.

The following example shows the incorrect structure for a multi-controller design where the second controller targets an RDIMM.

Existing code:


process(c1_ddr3_ck_p_sdram(0))
begin
if(rising_edge(c1_ddr3_ck_p_sdram(0))) then
if ( c1_ddr3_reset_n = '0' ) then
c1_ddr3_ras_n_r <= '1';
c1_ddr3_cas_n_r <= '1';
c1_ddr3_we_n_r <= '1';
c1_ddr3_cs_n_r <= (others => '1');
c1_ddr3_odt_r <= (others => '0');
end if;
else
c1_ddr3_addr_r <= c1_ddr3_addr_sdram after (SYSCLK_f0_PERIOD/2);
c1_ddr3_ba_r <= c1_ddr3_ba_sdram after (SYSCLK_f0_PERIOD/2);
c1_ddr3_ras_n_r <= c1_ddr3_ras_n_sdram after (SYSCLK_f0_PERIOD/2);
c1_ddr3_cas_n_r <= c1_ddr3_cas_n_sdram after (SYSCLK_f0_PERIOD/2);
c1_ddr3_we_n_r <= c1_ddr3_we_n_sdram after (SYSCLK_f0_PERIOD/2);
c1_ddr3_cs_n_r <= c1_ddr3_cs_n_sdram after (SYSCLK_f0_PERIOD/2);
c1_ddr3_odt_r <= c1_ddr3_odt_sdram after (SYSCLK_f0_PERIOD/2);
end if;
end process;


You will need to modify the code as follows:

Modified code:

process(c1_ddr3_ck_p_sdram(0))
begin
if(rising_edge(c1_ddr3_ck_p_sdram(0))) then
if ( c1_ddr3_reset_n = '0' ) then
c1_ddr3_ras_n_r <= '1';
c1_ddr3_cas_n_r <= '1';
c1_ddr3_we_n_r <= '1';
c1_ddr3_cs_n_r <= (others => '1');
c1_ddr3_odt_r <= (others => '0');
else
c1_ddr3_addr_r <= c1_ddr3_addr_sdram after (SYSCLK_f0_PERIOD/2);
c1_ddr3_ba_r <= c1_ddr3_ba_sdram after (SYSCLK_f0_PERIOD/2);
c1_ddr3_ras_n_r <= c1_ddr3_ras_n_sdram after (SYSCLK_f0_PERIOD/2);
c1_ddr3_cas_n_r <= c1_ddr3_cas_n_sdram after (SYSCLK_f0_PERIOD/2);
c1_ddr3_we_n_r <= c1_ddr3_we_n_sdram after (SYSCLK_f0_PERIOD/2);
c1_ddr3_cs_n_r <= c1_ddr3_cs_n_sdram after (SYSCLK_f0_PERIOD/2);
c1_ddr3_odt_r <= c1_ddr3_odt_sdram after (SYSCLK_f0_PERIOD/2);
end if;
end if;
end process;



NOTE: This Answer record applies to multi-controller designs where the second controller targets an RDIMM.

If a design targets an RDIMM with the first controller or targets multiple RDIMMs, you will need to modify the if-else statement within the pipelining logic appropriately.

This issue is fixed in the 13.1 MIG v3.7 software release.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
37173 MIG v3.6 - Release Notes and Known Issues for ISE Design Suite 12.3 N/A N/A

Associated Answer Records

AR# 37861
Date Created 09/03/2010
Last Updated 08/20/2014
Status Active
Type Known Issues
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
IP
  • MIG