A MIG GUI issue exists for specific multi-controller designs when the targeted package is the FF1760 (XC6VLX550T-FF1760, XC6VLX760-FF1760, XC6VLX550TL-FF1760 AND XC6VLX760L-FF1760) and the default banks are used. The issue is that MIG selects four columns for the Data group in the default bank selections which causes MIG to generate an invalid pin-out. The issue is seen by the following error in MAP:
"ERROR:Place:905 - Components driven by Regional clock net <2>> can't be placed and routed because location constraints are causing the clock region rules to be violated."
This issue only occurs in special scenarios for multi-controller designs; DDR3 SDRAM controller design with a frequency of 400 MHz or less and memory parts similar to the following:
* x4 component with data width of 72
* x8 component with data width of 144
* RDIMM whose base part is of x4 with data width of 72
There is no issue for single controller designs.
As an example, three controllers are selected in the GUI; among these one is a DDR3 controller and the other two are QDRII+ controllers. For the DDR3 controller, the frequency is 2500 ps and the memory part selected is MT18JSF51272PZ-1G4. In such a case, the data group is selected across four columns by default and the generated pin-out is invalid. Upon implementing the generated design it fails in MAP.
To work around this issue, re-generate your MIG design and manually select the banks; select "Deselect Banks" on the Bank Selection screen and manually enter the banks. When the banks are manually selected, the issues do not exist.