UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 37875

ML40x - LVDS support on the J5 connector

Description

Does the header J5 on the ML401/402/403 board support differential signaling?

Solution

The Expansion Differential Connectors header (J5), on the ML401/402/403, pinout is given in Table 9 of UG080:



The pins of this header connect to the FPGA I/O and can be used as independent single-ended nets as well as differential signaling, with one exception. Differential pair AD19-AC19 are lower capacitance clock pins that connect to Clock Capable I/Os. These pins do not support LVDS outputs, and become regular user I/Os when not needed for clocks.

When considering how to use the J5 header, it is important to realize that this differential pair does not support LVDS outputs.
AR# 37875
Date Created 09/06/2010
Last Updated 09/07/2010
Status Active
Type General Article
Devices
  • Virtex-4 SX
  • Virtex-4 LX
  • Virtex-4 FX