• ISE 12.3 software support

• Default simulation test has been upgraded
  • CR 571633, 532234
  • Default simulation test has been upgraded to include memory and I/O reads and writes.
• cfg_msg_* interface ports on Root Port Model now visible
  • CR 568527
  • cfg_msg_* ports are now visible at the top level of the Root Port Model delivered with Endpoint product.
• Syntax error in VHDL instantiation template
  • CR 572307
  • Syntax error in the VHDL instantiation template was corrected.
• User non-posted OK signal undriven in VHDL Root Port model
  • CR 568356
  • Issue resolved where the User non-posted OK signal was undriven in the VHDL Root Port model, preventing memory read transactions from passing to the User Interface.
• ACK Transmission Latency to Large
  • CR 565726
  • Issue resolved where the ACK transmission latency was to large, causing Replay timer on connected component trigger, thus generating an error.
• Missing simulation test restored
  • CR 558965
  • PCIe tests available in older cores / example designs, which were missing in older versions of the Spartan-6 core, have been restored.
• Class Code Lookup Assistant added
  • CR 525398
  • A Class Code Lookup Assistant has been added the GUI, to help determine the Class Code Values to be used.
• VHDL updates to ensure the Verilog and VHDL code were equivalent.
  • CR 555150
  • Verilog / VHDL equivalence formal check has been run to compare the Verilog and VHDL code for the wrappers.

Known Issues
(Xilinx Answer 36416) - Spartan-6 FPGA Integrated Block Wrapper v1.4 and v2.1 for PCI Express -User implemented configuration space registers starting addresses are not customizable
(Xilinx Answer 37595) -Spartan-6 Integrated Block Wrapper v2.1 and v1.4 for PCI Express - SIM_DEVICE attribute on RAMB16BWER is not set to "SPARTAN6"
(Xilinx Answer 38717) - Spartan-6 FPGA Integrated Block Wrapper for PCI Express v2.1 and v1.4 - Minimum sys_reset assertion length to properly reset the core
(Xilinx Answer 39548) - Spartan-6 FPGA Integrated Block Wrapper v2.2 and v1.4 for PCI Express - Replay Timeout is occurring too fast when using VHDL wrapper
(Xilinx Answer 42339) - Spartan-6 FPGA Integrated Block Wrapper v1.4 and v2.3 for PCI Express - What is the PMA_RX_CFG setting for an asynchronous link?
(Xilinx Answer 43576) - Spartan-6 FPGA Integrated Block for PCI Express - Updated GTP Attributes for v1.4 core version

Revision History
08/11/2011 - Added 42339, 43576
12/24/2010 - Added 39548
10/26/2010 - Added 37595,38717
10/05/2010 - Initial Release