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AR# 37939 Spartan-6 FPGA Integrated Block Wrapper for PCI Express (AXI) - Resolved issues in v2.1

Description

This article contains issues resolved in theSpartan-6 FPGA Integrated Block v2.1 Wrapper for PCI Express that are alsolisted in the readme.txt file that accompanies this version of the core. These are issues that were fixed as part of the update from the previous version of the core.

For other known and resolved issues that may not be in this list see(Xilinx Answer 45702).

Solution

Resolved Issues

  • Default simulation test has been upgraded
    • CR 571633, 532234
    • Default simulation test has been upgraded to include memory and I/O reads and writes.
  • cfg_msg_* interface ports on Root Port Model now visible
    • CR 568527
    • cfg_msg_* ports are now visible at the top level of the Root Port Model delivered with Endpoint product.
  • Syntax error in VHDL instantiation template
    • CR 572307
    • Syntax error in the VHDL instantiation template was corrected.
  • User non-posted OK signal undriven in VHDL Root Port model
    • CR 568356
    • Issue resolved where the User non-posted OK signal was undriven in the VHDL Root Port model, preventing memory read transactions from passing to the User Interface.
  • ACK Transmission Latency to Large
    • CR 565726
    • Issue resolved where the ACK transmission latency was to large, causing Replay timer on connected component trigger, thus generating an error.
  • Missing simulation test restored
    • CR 558965
    • PCIe tests available in older cores / example designs, which were missing in older versions of the S6 core, have been restored .
  • Class Code Lookup Assistant added
    • CR 525398
    • A Class Code Lookup Assistant has been added the GUI, to help determine the Class Code Values to be used.
Revision History
01/18/2012 - Modified format to use a single AR for all known issues and referenced 45702 for all known issues. Any issue that was listed here is now in AR 45702.
10/26/2010 - Added 37595, 38717
10/11/2010 - Added "AXI" designation to title for doc center.
10/05/2010 - Initial Release

Linked Answer Records

Child Answer Records

Answer Number Answer Title Version Found Version Resolved
39063 Spartan-6 FPGA Integrated Block for PCI Express - Why does trn_reset_n/user_reset_out(AXI) assert after sys_reset_n asserts? N/A N/A
37955 Spartan-6 FPGA Integrated Block for PCI Express - VHDL Wrapper Not Available for v2.1 Release N/A N/A
38717 Spartan-6 Integrated Block for PCI Express - Minimum sys_reset assertion length to properly reset the core N/A N/A
37595 Spartan-6 Integrated Block for PCI Express - SIM_DEVICE attribute on RAMB16BWER is not set to "SPARTAN6" N/A N/A
36416 Spartan-6 FPGA Integrated Block for PCI Express - User implemented configuration space registers starting addresses are not customizable N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
39063 Spartan-6 FPGA Integrated Block for PCI Express - Why does trn_reset_n/user_reset_out(AXI) assert after sys_reset_n asserts? N/A N/A
37955 Spartan-6 FPGA Integrated Block for PCI Express - VHDL Wrapper Not Available for v2.1 Release N/A N/A
36416 Spartan-6 FPGA Integrated Block for PCI Express - User implemented configuration space registers starting addresses are not customizable N/A N/A
37595 Spartan-6 Integrated Block for PCI Express - SIM_DEVICE attribute on RAMB16BWER is not set to "SPARTAN6" N/A N/A

Actions

AR# 37939
Date Created 09/10/2010
Last Updated 05/20/2012
Status Active
Type Release Notes
Devices
  • Spartan-6 LXT
Tools
  • ISE Design Suite - 12.3
IP
  • Spartan-6 FPGA Integrated Endpoint Block for PCI Express ( PCIe )
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