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AR# 37942

Virtex-5 and Virtex-6 Transceivers - DRC check in ISE 13.2 for reference clock forwarding to a tile or quad too far from the source


This answer record discusses the DRC check added in the ISE 13.2 software for reference clock forwarding.

A Virtex-6 or Virtex-5 FPGA design which previously ran successfully through ISE 12.x and 13.1tools now fails with a DRC errorin ISE 13.2 design tools. An example of this error message in the case of Virtex-6 FPGAis shown below:

"ERROR:PhysDesignRules - Invalid GTX dedicated clocking: The reach of a REFCLK coming from an IBUFDS element near another GTX and forwarded using dedicated routing is 6. Block core/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX (GTXE1_X1Y1) is more than that from its source clock."


This DRC check has been added starting with ISE 13.2 design toolsfor reference clocks forwarded two or more quads away from the source in Virtex-6 FPGA orfour or more tiles away from the source in Virtex-5 FPGA. Previously, the tools did not issue an error orwarning.

For more information on reference clock forwarding restrictions, refer to the Clocking section of the Transceiver User Guides for Virtex-5 and Virtex-6 FPGA Transceivers.

AR# 37942
Date 12/15/2012
Status Active
Type General Article
  • Virtex-6 HXT
  • Virtex-6 LXT
  • Virtex-6 SXT
  • More
  • Virtex-5 FXT
  • Virtex-5 LXT
  • Virtex-5 SXT
  • Virtex-5 TXT
  • Virtex-6 CXT
  • Less
  • ISE Design Suite - 12.2
  • ISE Design Suite - 12.3
  • ISE Design Suite - 12.4
  • More
  • ISE Design Suite - 13.1
  • ISE Design Suite - 12.1
  • Less
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