Starting with MIG 3.6 (available with ISE Design Suite 12.3), an additional calibration stage (CLKDIV Calibration Stage) is added to the calibration scheme performed upon reset.This new stage is in between stage 1 and stage 2 and is performed to calibrate the timing of the BUFIO to BUFR transfer.
Note: Xilinx recommends existing Virtex-6 DDR2/DDR3 designs upgrade to MIG 3.6 to have this calibration stage included.Details on this recommendation are noted below.
Note: This Answer Record is a part of the Xilinx MIG Solution Center(Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.