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AR# 3799

ngd2vhdl v1.4p ---Latest patch fixes 2-dimensional array problem and ROC pulse width


keywords: ngd2vhdl,Exemplar,Leonardo,2-dimensional,array,ROC,pulse.width

urgency: hot

general description:

The latest patch for ngd2vhdl:

fixes two problems. First, ngd2vhdl was incorrectly shorting nets together
if an array was referencing another array. This typically happened if a
customer was using the Exemplar synthesis toolset. Other synthesis tools
have been observed not to have this problem, since they write out arrays
in a different fashion.

Second, the user must now specify a pulse width for the ROC cell. The ROC
cell simulates the GSR/GR pusle of an FPGA during simulation. The default
pulse width in 1.4 is 0 ns, which causes VHDL simulators to not simulate.
Now, the user must specify the ROC width, using the -rpw option.



If you have downloaded the latest ngd2vhdl patch, and are now getting the

ERROR:basvh - A Reset-On-Configuration component is instantiated but no pulse
width is specified for it. In order to simulate ROC properly, the pulse width
for ROC must be specified with the command-line option -rpw.

This means that you must specify a non-zero pulse width for the ROC.

ngd2vhdl -rpw 10 design.nga

would create a 10 ns pulse width to simulate GR/GSR. This is a new feature
added to ngd2vhdl. This allows a user to change the GR/GSR width without
editing the VHDL file, and/or using a VHDL configuration.


If you are using the Exemplar tool set for VHDL synthesis, and the VHDL
code you have processed uses a 1-dimensional array to reference another
1-dimensional array, there will be a problem when simulating the design
with a .vhd file produced by ngd2vhdl. There are two solutions. The first
solution is to use a 2-dimensional array, instead of a 1-dimensional
array referencing another 1-dimensional array. The second solution is
to download the latest ngd2vhdl patch:

Xilinx Solution 3738
AR# 3799
Date Created 04/20/1998
Last Updated 04/03/2000
Status Archive
Type General Article