We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 37999

Aurora 64b/66b v4.1 - Simulation and Hardware always held in reset


Known Issue: v4.1

My Aurora core never seems to initialize and my MMCM never seems to lock. Why might this be happening in both simulation and hardware?


This is a result do to the PLLLKDET_*OUT_*LANE1 being ANDed with the tx_plllkdet_i. This should not be ANDed; instead, it should only depend on rx_plllkdet_i.

Make the proper change to the <core name >_wrapper.v[hd] so that the rx and tx plllkdet are not ANDed.

For example:
Change the following from:

PLLLKDET_OUT <= tx_plllkdet_i and rx_plllkdet_i;
plllkdet_i <= tx_plllkdet_i and rx_plllkdet_i;


PLLLKDET_OUT <= rx_plllkdet_i;
plllkdet_i <= rx_plllkdet_i;

Revision History
9/13/2010 - Initial Release
AR# 37999
Date Created 09/13/2010
Last Updated 10/28/2010
Status Active
Type General Article