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AR# 38016

Virtex-6 Program pin (PROG_B) does not delay configuration when held low at power up


The Virtex-6 architecture has changed the Program pin (PROG_B) behavior to an edge sensitive signal from a level sensitive signal.

What affect could this have on the system?


In Virtex-6, the Program pin (PROB_B) is level sensitive as opposed to edge sensitive. The falling edge of PROG_B needs to be seen by the Power On Reset (POR) circuitry to trigger house cleaning and an erasing of the device.
The PROG_B pin works as expected after power up and causes the device to be cleared and reset.

The difference in behavior occurs during power up. If the PROG_B pin is held Low prior to power up, the POR circuitry does not see a falling edge of the PROG pin. Therefore, holding PROG_B Low prior to power up does not delay configuration.

The INIT_B pin can always be used to delay configuration from power up. The INIT_B pin is an open drain driver and is released by the device when House Cleaning completes and the mode pins are ready to be sampled. Holding down this signal delays configuration as the mode pins are not sampled until a rising edge of INIT_B.

If need be, a diode can be used to connect the INIT_B pin to the PROG_B pin. This way, when PROG_B is pulled Low from the system, the INIT_B pin also is pulled Low. When the PROG_B pin is released, the device should still be able to drive INIT_B Low, overcoming the high signal from the diode. Post configuration, if INIT_B goes Low, the diode protects the PROG_B pin from seeing a low pulse. This method of using a diode needs to be tested to ensure INIT_B can drive to Vil when the diode is High, as well as making sure ViHmin can be met with the voltage drop over the diode.
AR# 38016
Date Created 09/14/2010
Last Updated 12/20/2010
Status Active
Type General Article
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