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AR# 3803

M1.4 CPLD - Fitter report & timing simulation (F1.4) gives incorrect equations.


Keywords: 1.4, cpld, equations

Urgency: Standard

General Description:

Example of the error -
1. Given a design is a top-level ABEL file for F1.4. Timing simulation & fitter
report give wrong results. Functional simualtion works correctly. In the ABEL code,
the equation & signals of concern is "ACK=ACKWR # (NB_RD_ACK)(RDCEN)"
In the fitter report under the equations section, ACK has a completely different equation.
2. In the ABEL code, ACKN=!ACK (sounds simple enough). But in the fitter report, ACKN=ACKN_BUFR


This problem is fixed in the latest M1.4 CPLD Tools Update
available on the Xilinx Download Area:


AR# 3803
Date Created 04/20/1998
Last Updated 03/29/2000
Status Archive
Type General Article