UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 38041

7.1i CPLDFit - The timespec on a clock divider output is not automatically adjusted

Description

The timespec on a clock divider output is not automatically adjusted.

Solution


The Clock Divider in the CoolRunner-II device can divide by 2, 4, 6, 8, 10, 12, 14 or 16.
The tools do not automatically adjust the period constraint to account for this. Therefore, if you are using the Clock Divider, you need to constraint for the output frequency of the Clock Divider.
AR# 38041
Date Created 09/16/2010
Last Updated 05/08/2014
Status Archive
Type General Article
Devices
  • CoolRunner-II