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AR# 38076

Block Memory Generator v4.3 - Release Notes and Known Issues for ISE 12.3

Description

This Release Notes and Known Issues Answer Record is for the Block Memory Generator v4.3 Core, released in ISE Design Suite 12.3, and contains the following information:

  • General Information
  • New Features
  • Bug Fixes
  • Known Issues
  • Technical Support

Solution

General Information

For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at:
http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf

For the most recent updates to the IP installation instructions for this core:
http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm

For system requirements:
http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm

This file contains release notes for the Xilinx LogiCORE IP Block Memory Generator v4.3 solution. For the latest core updates, see the product page at:
http://www.xilinx.com/products/ipcenter/Block_Memory_Generator.htm


Known Issues in v4.3
  • Virtex-6 FPGA Block RAM Memory collision error
  1. When the user selects TDP (write_mode= Read First)

    Impact: User will have to consider the collision issue
  • Spartan-6 FPGA Block RAM Memory collision error
  1. When the user selects TDP (write_mode= Read First)

    Impact: User will have to consider collision issue

    NOTE: Refer to UG383, 'Conflict Avoidance' section while using TDP Memory, with Write Mode = Read First in conjunction with asynchronous clocking.
  • Power estimation figures in the datasheet are preliminary
  • Core does not generate for large memories. Depending on the machine the ISE CORE Generator software runs on, the maximum size of the memory that can be generated will vary. For example, a Dual Pentium-4 server with 2 GB RAM can generate a memory core of size 1.8 MBits or 230 KBytes
  • CR 415768
  • (Xilinx Answer 24034) LogiCORE Block Memory Generator - Generating Block Memory Generator takes a long time
  • Out-of-range address input can cause the core to generate Xs on the DOUT bus
  • (Xilinx Answer 23744) LogiCORE Block Memory Generator - Invalid address on ADDR can cause the core to generate Xs on the DOUT bus during simulation
  • When the IP core is generated for Spartan-6 devices, the core should combine two adjacent 9k block RAM into one 18K block RAM.
  • CR 526429

Technical Support

To obtain technical support, create a WebCase at http://www.xilinx.com/support. Questions are routed to a team with expertise using this product. Xilinx provides technical support for use of this product when used according to the guidelines described in the core documentation, and cannot guarantee timing, functionality, or support of this product for designs that do not follow specified guidelines.
AR# 38076
Date Created 09/24/2010
Last Updated 09/27/2010
Status Active
Type Release Notes
Devices
  • Virtex-4 FX
  • Virtex-4 LX
  • Virtex-4 SX
  • More
  • Virtex-5 FXT
  • Virtex-5 LX
  • Virtex-5 LXT
  • Virtex-5 SXT
  • Virtex-5 TXT
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Spartan-3
  • Spartan-3 XA
  • Spartan-3A
  • Spartan-3A DSP
  • Spartan-3AN
  • Spartan-3E
  • Spartan-6 LX
  • Spartan-6 LXT
  • Less
Tools
  • ISE Design Suite - 12.3
IP
  • FIFO Generator