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AR# 38082

MIG v3.5, Spartan-6 - Selfrefresh Path - Synthesizing design fails in timing

Description

When using the Spartan-6 MCB in MIG v3.5, timing violations on "selfrefresh_enter" or "selfrefresh_mcb_mode" may be seen.

Below are two example for these timing errors.
 

Timing error example on selfrefresh_enter in .twr file:



Hold Paths: TS_u_OR_MIG_memc3_infrastructure_inst_clk_2x_180 = PERIOD TIMEGRP
"u_OR_MIG_memc3_infrastructure_inst_clk_2x_180" TS_CLK_OSC66M /
9.33333333 PHASE 0.812 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack (hold path): -1.243ns (requirement - (clock path skew + uncertainty - data path))
Source: u_OR_MIG/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/genblk288.gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/SELFREFRESH_MCB_REQ (FF)
Destination: u_OR_MIG/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0 (CPU)
Requirement: 0.000ns
Data Path Delay: 0.473ns (Levels of Logic = 0)
Clock Path Skew: 1.448ns (2.569 - 1.121)
Source Clock: u_OR_MIG/c3_mcb_drp_clk rising at 0.000ns
Destination Clock: u_OR_MIG/c3_sysclk_2x_180 falling at 1.623ns
Clock Uncertainty: 0.268ns

Clock Uncertainty: 0.268ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Discrete Jitter (DJ): 0.287ns
Phase Error (PE): 0.120ns

Minimum Data Path at Fast Process Corner: u_OR_MIG/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/genblk288.gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/SELFREFRESH_MCB_REQ to u_OR_MIG/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------------ -------------------
SLICE_X0Y112.BQ Tcko 0.234 u_OR_MIG/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/selfrefresh_mcb_enter
u_OR_MIG/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/genblk288.gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/SELFREFRESH_MCB_REQ
MCB_X0Y1.SELFREFRESHENTER net (fanout=2) 0.239 u_OR_MIG/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/selfrefresh_mcb_enter
MCB_X0Y1.PLLCLK1 Tmcbckd_SELFREFRESHENTER(-Th) 0.000 u_OR_MIG/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0
u_OR_MIG/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0
------------------------------------------------------ ---------------------------
Total 0.473ns (0.234ns logic, 0.239ns route)



Timing error example selfrefresh_mcb_mode  in .twr file:

Paths for end point LOGIC_TOP1/DRAMC1/MIG1/memc3_wrapper_inst/mcb_ui_top_inst/mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Mshreg_SELFREFRESH_MCB_MODE_R2 (SLICE_X2Y48.DX), 1 path
--------------------------------------------------------------------------------
Slack (setup path): -1.677ns (requirement - (data path - clock path skew + uncertainty))
Source: LOGIC_TOP1/DRAMC1/MIG1/memc3_wrapper_inst/mcb_ui_top_inst/mcb_raw_wrapper_inst/samc_0 (CPU)
Destination: LOGIC_TOP1/DRAMC1/MIG1/memc3_wrapper_inst/mcb_ui_top_inst/mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Mshreg_SELFREFRESH_MCB_MODE_R2 (FF)
Requirement: 1.250ns
Data Path Delay: 1.838ns (Levels of Logic = 0)(Component delays alone exceeds constraint)
Clock Path Skew: -0.881ns (1.509 - 2.390)
Source Clock: LOGIC_TOP1/DRAMC1/MIG1/c3_sysclk_2x_180 rising at 8.749ns
Destination Clock: LOGIC_TOP1/CLK_DRAMC rising at 9.999ns
Clock Uncertainty: 0.208ns

Clock Uncertainty: 0.208ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Discrete Jitter (DJ): 0.160ns
Phase Error (PE): 0.120ns

Maximum Data Path at Slow Process Corner: LOGIC_TOP1/DRAMC1/MIG1/memc3_wrapper_inst/mcb_ui_top_inst/mcb_raw_wrapper_inst/samc_0 to LOGIC_TOP1/DRAMC1/MIG1/memc3_wrapper_inst/mcb_ui_top_inst/mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Mshreg_SELFREFRESH_MCB_MODE_R2
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
----------------------------------------------------- -------------------
MCB_X0Y1.SELFREFRESHMODE Tmcbcko_SELFREFRESHMODE 1.000 LOGIC_TOP1/DRAMC1/MIG1/memc3_wrapper_inst/mcb_ui_top_inst/mcb_raw_wrapper_inst/samc_0
LOGIC_TOP1/DRAMC1/MIG1/memc3_wrapper_inst/mcb_ui_top_inst/mcb_raw_wrapper_inst/samc_0
SLICE_X2Y48.DX net (fanout=1) 0.938 LOGIC_TOP1/DRAMC1/MIG1/memc3_wrapper_inst/mcb_ui_top_inst/mcb_raw_wrapper_inst/selfrefresh_mcb_mode
SLICE_X2Y48.CLK Tds -0.100 LOGIC_TOP1/DRAMC1/DRAMC_REG1/CLR5/SYNC_CLREN
LOGIC_TOP1/DRAMC1/MIG1/memc3_wrapper_inst/mcb_ui_top_inst/mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/Mshreg_SELFREFRESH_MCB_MODE_R2
----------------------------------------------------- ---------------------------
Total 1.838ns (0.900ns logic, 0.938ns route)
(49.0% logic, 51.0% route)





Solution

These errors can occur under the following two conditions:

  1. If Selfrefresh mode is used.
     
    In this case, the path is expected to fail in timing because it is a cross clock domain.
     
  2. If Selfrefresh is not used and Synplify is used as synthesis tool.
     
    When the Synplify option "no_sequential_opt 1" is used, the path will not be trimmed during synthesis and the timing errors occurs.
     
    In this case you can either ignore the timing error or ignore the path as in the following example:
     
    NET "memc?_wrapper_inst/memc?_mcb_raw_wrapper_inst/selfrefresh_mcb_req" TIG;
AR# 38082
Date Created 09/16/2010
Last Updated 08/27/2014
Status Active
Type Error Message
Devices
  • Spartan-6
Tools
  • ISE Design Suite
IP
  • MIG