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AR# 38087

14.x Timing - How do I analyze the input/output paths timing if I did not add OFFSET IN/OUT constraint in UCF?

Description

If I did not add OFFSET IN/OUT constraints in UCF, how do I analyze the input/output paths timing in Timing Analyzer?

Solution

You can use one of the following ways:

  • Use "user specified paths by defining endpoints" analysis; see (Xilinx Answer 2742).
  • Use "auto-generated timing constraints" analysis. Follow these steps:
    1. In ISE, expand the tree for Implement Design -> Place and Route -> and Generate Post-Place and Route Static Timing.
    2. Double-click on Analyze Post-Place and Route Static Timing (Timing Analyzer).
    3. Select Timing -> Run Timing Analysis, and select Analysis against: auto-generated timing constraints.
    4. Use Filter by Net to narrow down your analysis.
  • Use "user specified paths by defining clock and I/O timing" analysis. Follow these steps:
    1. In ISE, expand the tree for Implement Design -> Place and Route -> and Generate Post-Place and Route Static Timing.
    2. Double-click on Analyze Post-Place and Route Static Timing (Timing Analyzer).
    3. Select Timing -> Run Timing Analysis, and select Analysis against: user specified paths by defining clock and I/O timing.
    4. Specify the requirements you want to add to the design.
    5. Use Filter by Net to narrow down your analysis.
AR# 38087
Date Created 10/10/2011
Last Updated 12/15/2012
Status Active
Type General Article
Tools
  • ISE Design Suite - 11.1
  • ISE Design Suite - 11.2
  • ISE Design Suite - 11.3
  • More
  • ISE Design Suite - 11.4
  • ISE Design Suite - 11.5
  • ISE Design Suite - 12.1
  • ISE Design Suite - 12.2
  • ISE Design Suite - 12.3
  • ISE Design Suite - 13.1
  • ISE Design Suite - 13.2
  • ISE Design Suite - 13.3
  • ISE Design Suite - 12.4
  • ISE Design Suite - 13.4
  • ISE Design Suite - 14.1
  • Less