It is common for designs to have one or more divided clocks. There are different ways to divide a clock and it is recommended that you use a clock management component, such as an MMCM to achieve the division. In this situation, the tool propagates the period constraint to the divided clock, for example, CLKDV and any multicycle path is also constrained automatically by the tool.
But, for a number of reasons, you might optout ofusing of an MMCM. In these cases, you normally use gated clocks for the division.Because gated clocks generally are implemented using flip flops and look up tables, the tool does not propagate the period constraint on the input clock and as a result, the divided clock is left unconstrained and the you need to constrain these clocks.
The next diagram shows an example of a divider circuit using four flip flops and one inverter.
To constrain this kind of clock, add a period on the clock input as:
NET "CLKIN" TNM_NET = CLKIN;
TIMESPEC TS_CLKIN = PERIOD "CLKIN" 10 ns HIGH 50%;
Then, apply a period on the clock out and relate it to the clock in manually as:
NET "CLKOUT" TNM_NET = CLKOUT;
TIMESPEC TS_CLKOUT = PERIOD "CLKOUT" TS_CLKIN*16 PHASE XYZ ns;
The value 16 is the division factor brought by the divider circuit, while the PHASE XYZ is the delay edge relation between CLKIN and CLKOUT. This phase is actually the delay from the output pin of component, which generates CLKIN to the output clock pin of FF4. The delay includes the switching delay from clock to Q output of all four FFs as well as the routing delays from FF to the next, shown in red in the diagram.
Because the phase depends on the routings, everytime something is changed in the design (even constraints) the routing delays change, and, therefore, it affects the PHASE XYZ. This needs to be fixed at a certain value. This is done in two ways:
You can compute the delay using the FPGA Editor (selecting pins and pressing the 'delay' button) or Timing Analyzer (endpoint-to-endpoint analysis).