One of the comments in the MIG-generated V6 DDR2/DDR3 UCF is incorrect:
Currently:
# Signal to select between controller and physical layer signals. Four divided by two clock
# cycles (8 memory clock cycles) are provided by design for the signal to settle down.
# Used only by the phy modules.
INST "u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/u_ff_phy_init_data_sel" TNM = "TNM_PHY_INIT_SEL";
TIMESPEC "TS_MC_PHY_INIT_SEL" = FROM "TNM_PHY_INIT_SEL" TO FFS = "TS_sys_clk"*4;
In the comments above, "(8 memory clock cycles)" should be changed to "(4 memory clock cycles)" to reflect the value of the constraint.
Should be:
# Signal to select between controller and physical layer signals. Four divided by two clock
# cycles (4 memory clock cycles) are provided by design for the signal to settle down.
# Used only by the phy modules.
INST "u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/u_ff_phy_init_data_sel" TNM = "TNM_PHY_INIT_SEL";
TIMESPEC "TS_MC_PHY_INIT_SEL" = FROM "TNM_PHY_INIT_SEL" TO FFS = "TS_sys_clk"*4;
This is fixed in the ISE 13.1 MIG v3.7 software release.