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AR# 38125

MIG v3.6, Virtex-6 DDR2/DDR3 - Comments in the UCF are incorrect

Description

One of the comments in the MIG-generated V6 DDR2/DDR3 UCF is incorrect:

Currently:

# Signal to select between controller and physical layer signals. Four divided by two clock
# cycles (8 memory clock cycles) are provided by design for the signal to settle down.
# Used only by the phy modules.
INST "u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/u_ff_phy_init_data_sel" TNM = "TNM_PHY_INIT_SEL";
TIMESPEC "TS_MC_PHY_INIT_SEL" = FROM "TNM_PHY_INIT_SEL" TO FFS = "TS_sys_clk"*4;

Solution

In the comments above, "(8 memory clock cycles)" should be changed to "(4 memory clock cycles)" to reflect the value of the constraint.

Should be:
# Signal to select between controller and physical layer signals. Four divided by two clock
# cycles (4 memory clock cycles) are provided by design for the signal to settle down.
# Used only by the phy modules.
INST "u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/u_ff_phy_init_data_sel" TNM = "TNM_PHY_INIT_SEL";
TIMESPEC "TS_MC_PHY_INIT_SEL" = FROM "TNM_PHY_INIT_SEL" TO FFS = "TS_sys_clk"*4;


This is fixed in the ISE 13.1 MIG v3.7 software release.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
37173 MIG v3.6 - Release Notes and Known Issues for ISE Design Suite 12.3 N/A N/A

Associated Answer Records

AR# 38125
Date Created 09/21/2010
Last Updated 05/20/2012
Status Archive
Type Known Issues
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
IP
  • MIG