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AR# 38134

Design Advisory for Virtex-6 Configuration - PROGRAM_B pin held Low prior to power up does not delay configuration


How can configuration be delayed at power up on a Virtex-6 device, and how is this different from prior families?


On prior families the PROG or the INIT pins can be held low at power-up to delay configuration. With the Virtex-6 devices the PROG pin is edge sensitive as opposed to level sensitive. So, holding this pin low at power up will not continue to delay configuration.

The way to delay configuration is to hold the INIT pin low. INIT is an open drain driver and requires a pullup on the pin to pull the pin high once it is released by the device. The device will only drive the pin low, and will then release the pin when the device is ready to start configuration. The INIT pin must then go high for the mode pins to be sampled and the configuration process to begin.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
34565 Design Advisory Master Answer Record for Virtex-6 FPGA N/A N/A

Child Answer Records

Answer Number Answer Title Version Found Version Resolved
38016 Virtex-6 Program pin (PROG_B) does not delay configuration when held low at power up N/A N/A

Associated Answer Records

AR# 38134
Date Created 09/27/2010
Last Updated 10/15/2012
Status Active
Type Design Advisory
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less