We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 38141

CoolRunner-II Timing - Bi-directional signals can have the wrong results in Timing Analyser


When I look at the timing report for a Bi-Directional signal it appears to have passed, but when the delays are calculated it actually has failed.
Why is the failure not highlighted?


This is a known issue. Following is an example of an incorrectly reported path:

Timing constraint: TS_TEST: FROM:TCK_G1:TO:TCK_G2:10.000nS

Slack: 6.500ns (requirement - data path)
Source: In_Pin
Destination: Out_Pin
Requirement: 10.000ns
Data Path Delay: 3.500ns (Levels of Logic = 6)

Data Path: In_Pin to Out_Pin
Location Delay type Delay(ns) Logical Resource(s)

In_Pin - 0.000 In_Pin
In_Pin.ZIA tIN + tHYS25 5.600 In_Pin.ZIA
Out_Pin.Q tLOGI1 + tLOGI2 + tPDI 2.300 Out_Pin.Q
Out_Pin tOUT + tOUT25 3.500 Out_Pin

The delay is listed as 3.5nS which gives a slack of 6.5nS, but the path is actually 5.6 + 2.3 + 3.5 = 11.4ns, so the constraint should have failed with a slack of -1.4nS.

To work around this issue,use the ASCII report (which correctly analyzes). The ASCII report can be generated by running the following in the command line:

taengine -f design_name .vm6 -detail
AR# 38141
Date Created 09/28/2010
Last Updated 12/15/2012
Status Active
Type General Article
  • CoolRunner-II
  • CoolRunner-II XA