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AR# 38181

Architecture Wizard - Glitches produced on RST port of cascaded DCM


I have used one of the Cascaded DCM wizards to build a cascaded DCM solution that will yield the clock frequencies I need for my design. However, when I simulate the design, I see the following error during functional and timing simulation:

Error: Input Error : RST on DCM_?SP must be asserted for 3 CLKIN clock cycles.

I can verify that the logic needed for the reset pin has been successfully implemented.

Will this glitch present an issue in hardware? How can I remove this error?


This situation can occur if the second DCM is sourced by one of the DLL outputs of the first DCM.

To resolve this issue,

1) If you are using an .xaw file in your design, remove the file and instead add the HDL equivalent.
2) Insert an FD primitive between the output of the OR2 gate and the RST pin of the cascaded DCM.

Adding a flip-flop will prevent any glitches introduced by the reset logic to propagate to the reset pin of the DCM.

AR# 38181
Date Created 09/22/2010
Last Updated 01/05/2011
Status Active
Type General Article
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