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AR# 38211

SPI-4.2 v10.2 - Release Notes and Known Issues for ISE Design Suite 12.3


This Release Notes and Known Issues Answer Record is for the SPI-4.2 (POS-PHY L4) v10.2 Core (released in ISE Design Suite12.3) and the v10.2 rev1 Core (released as a patch below), and contains the following information:
  • New Features
  • Resolved Issues
  • General Information
  • Known Issues
  • Patch
For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at:


New Features in v10.2
  • ISE 12.3 software support
  • Support new split I/O clocking feature for Spartan-6 FPGA designs
  • Increase performance limits for Virtex-6 FPGA cores with Dynamic Alignment configuration when configured with regional clock scheme. These higher performances are only for v10.2 cores and onwards with ISE 12.3 and later software.
  • Optimize Virtex-6 FPGA block RAM utilization by using Simple Dual Port RAM with WRITE_FIRST mode.
Resolved Issues in v10.2
Resolved Issues in v10.2rev1
  • (Xilinx Answer 38399) - SPI-4.2 v10.2 - Virtex-6 FPGAs Global Clocking support for source core removed when using static alignment
  • (Xilinx Answer 38400) - SPI-4.2 v10.2 - Reduced performance of Virtex-6 FPGA Source core with global clocking when the receiver Sink core is configured with dynamic phase alignment

General Information
  • (Xilinx Answer 37917) LogiCORE SPI-4.2 - Input clocking requirement for source reference clock (SysClk)
  • Updated performance of Virtex-6 source core as follows:
  • (Xilinx Answer 32917) Virtex-6 FPGA change to HIGH_PERFORMANCE_MODE attribute for IODELAYE1 elements in UCF
  • If you are using multiple SPI-4.2 Cores in a single device, you must generate the core with a unique component name for each instance. See the Multiple Core Instantiation section under the Special Design Considerations chapter of the SPI-4.2 User Guide.
  • Xilinx Answer 15500) How do I edit the SPI-4.2 (PL4) UCF file so that the TSClk is skewed by 180 degrees in the DCM?
  • (Xilinx Answer 20017) Which I/O Standards are supported for the SPI-4.2 Core?
  • (Xilinx Answer 32942) Changing static configuration signals in-circuit
  • Sink DPA Clock Adjustment option for Global Clocking Mode is not supported for Virtex-6 devices

Known issues in v10.2rev1
  • (Xilinx Answer 39106)- SPI-4.2 Spartan-6 Device Support has been removed
  • (Xilinx Answer 38214) - SPI-4.2 v10.1 and v10.2 - Missing constraints in ucf file when targeting Virtex-6 FPGAs
  • (Xilinx Answer 34629) - Spartan-6 FPGA example design might fail timing on RStat pins
  • (Xilinx Answer 35270) - SPI-4.2 & SPI-4.2 Lite - Documentation does not describe behavior when partial credit is written
  • (Xilinx Answer 38869) - SPI-4.2 v10.2 and earlier - Sink core static configuration signal, FifoAFMode, is not set correctly by the GUI
  • (Xilinx Answer 38870) -SPI-4.2 v10.2 and earlier - Updated example MMCM instantiation needed to follow new restriction for DIVCLK_DIVIDE

Constraints and Implementation Issues
  • (Xilinx Answer 20000) - When implementing an SPI-4.2 design through NGDBuild, several "WARNING" and "INFO" messages appear
  • (Xilinx Answer 21439) - When implementing an SPI-4.2 design through MAP, several "WARNING" and "INFO" messages appear
  • (Xilinx Answer 21320) - When implementing an SPI-4.2 design through PAR, several "WARNING" and "INFO" messages appear
  • (Xilinx Answer 21363) - PAR has problems placing components or completely routing the SPI4.2 design in my design
  • (Xilinx Answer 20280) - Placement failures occur in PAR when the SPI-4.2 FIFO Status Signals' I/O Standard is set to LVTTL I/O
  • (Xilinx Answer 20040) - Timing Analyzer (TRCE) reports "0 items analyzed"
  • (Xilinx Answer 20319) - When running implementation, undefined I/O (single-ended) defaults to LVCMOS causes WARNINGS in NGDBuild

General Simulation Issues
  • (Xilinx Answer 24026) - When I run simulation on SPI-4.2 design, Locked_RDClk (from RDClk DCM) might get de-asserted after PhaseAlignRequest
  • (Xilinx Answer 21319) - When I run timing simulation on an SPI-4.2 design example, several "TDat Error: Data Mismatch" messages are reported
  • (Xilinx Answer 21321) - Timing simulation error: # ** Error: */X_ISERDES SETUP Low VIOLATION ON D WITH RESPECT TO CLK;
  • (Xilinx Answer 21322) - When I run timing simulation on a SPI4.2 design, several SETUP, HOLD, and RECOVERY violations occur
  • (Xilinx Answer 20030) - When I simulate an SPI-4.2 design, multiple warning messages are expected at the beginning of the simulation
  • (Xilinx Answer 15578) - When I simulate an SPI-4.2 (PL4) Core using NC-Verilog (by Cadence) or VCS (by Synopsys), unusual and inconsistent behaviors occur
  • (Xilinx Answer 35266) - NCSIM Warnings 12.1:ncelab: *W,SDFINF: Instance XIL_ML_UNUSED_DCM_1/CLKFB not found at scope level, line.

      Download Rev1 update

      To get the mandatory Rev1 update for Spartan-6 and Virtex-6 FPGAs with resolved issues described above, apply the following patch to the Xilinx ISE 12.3 software installation:


      Install the patch by extracting the contents of the ".zip" archive to the root directory of the Xilinx ISE 12.3 software installation. Select the option that allows the extractor to overwrite all of the existing files and maintain the directory structure predefined in the archive.

      After installing the patch, regenerate the SPI-4.2 (POS-PHY L4) v10.2 Core in CORE Generator tool. For further information on finding the Xilinx install and using environment variables, see (Xilinx Answer 11630).

      NOTE: You might be required to have system administrator privileges to install the patch if you do not have write permissions to the Xilinx Install directory.

      Revision History
      10/05/2010 - Initial Release
      12/02/2010 - Added Answer Record 37917

      Linked Answer Records

      Child Answer Records

      AR# 38211
      Date 05/20/2012
      Status Active
      Type Release Notes
      • SPI-4 Phase 2 Interface Solutions
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