Refer to this Answer Record for help resolving "HDLCompiler:718: Port connections cannot be mixed ordered and named" errors.
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This message appears when both ordered and named port connections are used for a module instantiation in Verilog. This is not allowed. An instantiation in Verilog should use either named or ordered connections.
WHAT NEXT:
Modify the instantiations to use either the named connections or ordered connections; in other words, do not mix them.
EXAMPLE:
Consider the following RTL:
module top(i, o);
input i;
output o;
test inst(i, .out(o));
endmodule
module test(in, out);
input in;
output out;
endmodule
In the instantiation of module 'test', two port connections have been used. The first portis ordered connection, the secondis named connection. This is not allowed.