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AR# 38301

CoolRunner-II Timing - Is the tCYC of a dual edge trigger register correctly analyzed?

Description

Is the tCYC of a dual edge trigger register correctly analyzed?

Solution


The definition of the Clock to Setup (tCYC) in the CPLD timing report states:
Register to register cycle time. Includes source register tCO and destination register tSU.
NOTE: When the computed Maximum Clock Speed is limited by tCYC, it is computed assuming that all registers are rising-edge sensitive.
Therefore, when you are using a dual edge trigger register, the tCYC only takes the rising-edge into account.
AR# 38301
Date Created 09/28/2010
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • 9500
  • 9500XL
  • 9500XL IQ
  • More
  • 9500XL XA
  • 9500XV
  • CoolRunner XPLA3
  • CoolRunner-II
  • CoolRunner-II XA
  • Less