We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 38340

12.x ChipScope Pro, IBERT, Virtex-5, GTX - Line rate is displayed incorrectly and links are down


I generate my IBERT GTX core with a 32-bit data width and 2.0G line rate. When I pull up the Analyzer, the line rate is detected from the divider settings as 2.5G, and all the links are down. What is the issue here? How can I get the links to work?


The INTDATAWIDTH port is improperly set to 1 (div by 5) when it should be 0 (div by 4). Setting that value manually in the Port settings tab causes the channels to immediately link. This issue is resolved in ChipScope Pro 12.4.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
35269 12.x ChipScope Pro - Known Issues for the ChipScope Pro 12.x software N/A N/A
AR# 38340
Date Created 09/29/2010
Last Updated 01/02/2013
Status Active
Type General Article
  • Virtex-5 FXT
  • ChipScope Pro - 11.3
  • ChipScope Pro - 11.4
  • ChipScope Pro - 11.5
  • More
  • ChipScope Pro - 11.1
  • ChipScope Pro - 11.2
  • ChipScope Pro - 12.1
  • ChipScope Pro - 12.2
  • ChipScope Pro - 12.3
  • Less
  • ChipScope Pro IBERT for Virtex-5 GTX