The 10G Ethernet IP Design Assistant will walk you through the recommended design flow while debugging commonly encountered issues, such as simulation issues, link failures, and data errors. The Design Assistant will not only provide useful design and troubleshooting information, but also point you to the exact documentation you need to read to help you design efficiently with the 10G Ethernet IP. IP included are the 10G Ethernet MAC, XAUI, RXAUI, and 10G PCS/PMA cores.
NOTE: This answer record is part of the Ethernet IP Solution Center (Xilinx Answer 38279). The Ethernet IP Solution Center is available to address all questions related to Ethernet IP. Whether you are starting a new design with Ethernet IP cores or troubleshooting a problem, use the Ethernet IP Solution Center to guide you to the right information.
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 38279 | Ethernet IP Solution Center | N/A | N/A |
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 38386 | 10G Ethernet IP Design Assistant - Hardware Debug and Link Bring up | N/A | N/A |
| 38385 | 10G Ethernet IP Design Assistant - Synthesis and Implementation | N/A | N/A |
| 38348 | 10G Ethernet IP Design Assistant - Simulation Debug | N/A | N/A |
| 33596 | LogiCORE IP XAUI - Frequently Asked Questions (FAQ) | N/A | N/A |
| 38279 | Ethernet IP Solution Center | N/A | N/A |