We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 38386

10G Ethernet IP Design Assistant - Hardware Debug and Link Bring up


This answer record identifies starting points when debugging hardware and link bring up issues with the 10G Ethernet IP.

Note: This Answer Record is a part of the Ethernet IP Solution Center (Xilinx Answer 38279).The Ethernet IP Solution Center is available to address all questions related to Ethernet IP. Whether you are starting a new design with Ethernet IP cores or troubleshooting a problem, use the Ethernet IP Solution Center to guide you to the right information.


The Debugging Designs Chapter at the end of the XAUI and RXAUI User Guide has a Hardware debug section with guidance on:

  • General Checks for Hardware Debug
  • Monitoring the XAUI Core with ChipScope Tool
  • Problems with Data Reception or Transmission
  • What Can Cause a Local or Remote Fault?
  • Link Bring Up
  • What Can Cause Synchronization and Alignment to Fail?
  • What Can Cause the XAUI Core to Insert Errors?
  • Problems with the MDIO

These Guides are available at the below links:

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
38279 Ethernet IP Solution Center N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
38343 Ethernet IP Solution Center - 10G Ethernet IP Design Assistant N/A N/A
AR# 38386
Date Created 10/08/2010
Last Updated 02/24/2013
Status Active
Type General Article
  • 10 Gigabit Ethernet Media Access Controller
  • XAUI