When I build a system with the AXI_DMA, AXI_VDMA, or AXI_CDMA core in a 6-series military-grade device (Spartan-6Q, Virtex-6Q or Spartan-6QI FPGA) or Virtex-6 CX device, the following error occurs:
"ERROR:Xst:2647 - Failed to run core generator for <testinst_wrapper_fifo_generator_v6_1_1> macro."
The XST error has also occurs when the XPS_LL_TEMAC parameter C_TEMAC_TYPE = 2 (Soft), and the C_TEMAC0_TXCSUM and C_TEMAC0_RXCSUM are set to 1 which enables the checksum off load logic. The error in the XST ".srp" file is as follows:
"Exception in thread "main" java.lang.RuntimeException: XST has returned an error: ERROR:HDLCompiler:0 - "Unknown" Line 0: cannot open file "e:/</projects/xilinx/sp605_reference/rdf0088/sp605_embedded_kit/sp605_system/hw/microblaze_processor_
subsystem_phyter_chksum/implementation/soft_temac_wrapper_fifo_generator_v6_1_1_fifo_generator_v6_1_xst_1_xsd/
fifo_generator_v6_1/fifo_generator_v6_1.vdbl" for writing"
How do I resolve this issue?
A work-around that has fixed the issuewas to move the XPS source files to a different directory.
This issue has been fixed starting in EDK 12.4.