UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 38396

Virtex-6 FPGA GTX Transceiver Wizard v1.7 - Release Notes and Known Issues for ISE Software 12.3

Description

This Answer Record contains the release notes and known issues for the Virtex-6 GTX Transceiver Wizard v1.7 released with ISE Design Suite 12.3.

Solution

1. INTRODUCTION

For the most recent updates to the IP installation instructions for this
core, please go to:

   http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm

For system requirements:

   http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm

This file contains release notes for the Xilinx LogiCORE IP Virtex-6 FPGA GTX
Transceiver Wizard v1.7 solution. For the latest core updates, see the product
page at:

   http://www.xilinx.com/content/xilinx/en/products/intellectual-property/v6_fpga_gtx_transceiver_wizard.html

2. NEW FEATURES

- ISE 12.3 software support

3. SUPPORTED DEVICES
 
The following device families are supported by the core for this release.

Virtex-6 XC CXT/LXT/SXT/HXT
Virtex-6 XQ LXT/SXT                                                      
Virtex-6 -1L XC LXT/SXT

4. RESOLVED ISSUES

- CR 564926, 570699

5. KNOWN ISSUES

The following are known issues for v1.6 of this core at time of release:

- The transceiver attributes are not validated on the latest production silicon

- When the RX Buffer is bypassed, the RX delay aligner logic uses the DRP Port. Currently, there is no arbitration logic to enable user accesses for the DRP when RX delay aligner is active. The RX delay aligner logic is enabled for line rates 2.4GHz and above. This logic works for silicon revision 2.0 and above.

The most recent information, including known issues, workarounds, and resolutions for this version is provided in the IP Release Notes Guide
located at
   www.xilinx.com/support/documentation/user_guides/xtp025.pdf

6. TECHNICAL SUPPORT

To obtain technical support, create a WebCase at www.xilinx.com/support. Questions are routed to a team with expertise using this product.

Xilinx provides technical support for use of this product when used according to the guidelines described in the core documentation, and cannot guarantee timing, functionality, or support of this product for designs that do not follow specified guidelines.

7. OTHER INFORMATION

- Display Port, Fiber Channel 1G, 2G, 4G, OC48, SATA-I and SATA-II protocol files are not tested for compliance
- For Display Port protocol, set TX/RXPLL_DIVSEL_FB=2, TX/RXPLL_DIVSEL_REF=1, TX/RXPLL_DIVSEL_OUT=1
- For SATA-II protocol, set TX/RXPLL_DIVSEL_FB=2, TX/RXPLL_DIVSEL_REF=2, TX/RXPLL_DIVSEL_OUT=1
- The transceiver attributes of v1.7 version of this core support 2.01 silicon
  revision

 

8. CORE RELEASE HISTORY

Date        By            Version      Description
================================================================================
09/21/2010  Xilinx, Inc.  1.7          ISE 12.3 support
07/23/2010  Xilinx, Inc.  1.6          ISE 12.2 support
04/19/2010  Xilinx, Inc.  1.5          ISE 12.1 support
12/02/2009  Xilinx, Inc.  1.4          ISE 11.4 support
09/16/2009  Xilinx, Inc.  1.3          ISE 11.3 support
06/24/2009  Xilinx, Inc.  1.2          ISE 11.2 support
04/24/2009  Xilinx, Inc.  1.1          ISE 11.1 support
================================================================================

 

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
33475 Virtex-6 FPGA GTX Transceiver - Known Issues and Answer Record List N/A N/A
AR# 38396
Date Created 04/18/2011
Last Updated 11/10/2014
Status Active
Type General Article
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LXT
  • Virtex-6 SXT
IP
  • Virtex-6 FPGA GTX Transceiver Wizard