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AR# 38409

Aurora 8B/10B v6.1 - Release Notes and Known Issues for ISE Design Suite 12.3


This Answer Record contains the Release Notes for the Aurora 8B/10B v6.1 Core, released in ISE 12.3, and includes the following:

- General Information
- New Features
- Bug Fixes
- Known Issues

For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at:



New Features

  • AXI4-Stream Support. The LogiCORE IP Aurora 8B/10B v6.1 core implements the AMBA protocolAXI4-Stream user interface
  • ISE 12.3 software support

Bug Fixes

  • implement AR #35681- Virtex-6 GTX Transceiver - MMCM fails to lock andTX/RXRESETDONE fails to assert
    CR number 571131
  • CLOCK_HOLD has to be set TRUE in MMCM for Virtex-6/Virtex-6L/Virtex-6Q FPGA
    CR number 571126
  • Update Virtex-6 CXT GT PLL range with latest value from DS153
    CR number 564690
  • Sidebands signals should be removed for timer based Simplex designs
    CR number 523320

Known Issues

  • MAP issues DRC error from ISE 12.3 for the Virtex-5 GTP/GTX Aurora 8B10B design which has unused transceiver(s) [GTP_DUAL or GTX_DUAL].
    Refer AR# 33473 [ http://www.xilinx.com/support/answers/33473.htm ] for workaround.
    CR number 571309
  • Timing errors observed for designs with transceivers selected noncontinuously.
    Refer Appendix B in LogiCORE IP Aurora 8B10B v6.1User Guide - UG766 for more details.
    CR Number 532828
AR# 38409
Date Created 01/05/2011
Last Updated 05/19/2012
Status Active
Type Release Notes
  • Aurora 8B/10B