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AR# 38430

Design Assistant for PCI Express - Simulation Questions Regarding Link Training

Description


This Answer Record identifies starting points when debugging simulation link training related issues to PCI Express.
NOTE: This Answer Record is part of the Xilinx Solution Center for PCI Express (Xilinx Answer 34536) The Xilinx Solution Center for PCI Express is available to address all questions related to PCIe. Whether you are starting a new design with PCIe or troubleshooting a problem, use the Solution Center for PCIe to guide you to the right information.

Solution

The various timeouts contained within the LTSSM states are reduced for simulation. This allows for a shorter link training time and speeds up overall simulation. When using third party BFMs, it is often helpful to know these values. The timeout values are documented in the PCI Express User Guides. For links to these guides, see(Xilinx Answer 35920) />
Revision History
10/11/2010 - Initial Release

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
38548 Design Assistant for PCI Express - Simulation Traffic Questions N/A N/A
35107 Design Assistant for PCI Express - Simulation Debug N/A N/A
AR# 38430
Date Created 10/13/2010
Last Updated 12/15/2012
Status Active
Type General Article
IP
  • Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )
  • Endpoint Block Plus Wrapper for PCI Express
  • Spartan-6 FPGA Integrated Endpoint Block for PCI Express ( PCIe )