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AR# 38468

12.1 Timing Analysis - Virtex5 - IODELAY inference results in different TRCE number than in table 91 of DS202


I created a testcase with IFD and BUFG, as described in the Table 91 of Virtex-5 FPGA Data Sheet (DS202), but the setup and hold times do not match the data sheet table values. Why?



An issue has been seen with an IFD and BUFG in a simple testcase to match the description of Table 91 of Virtex-5 Data Sheet (DS202). Pack uses the IDELAY as a route-thru instead of fully utilizing the IDELAY. The route-thru has more delay than the "Default" IDELAY value, which causes the timing analysis to not match the data sheet (DS202; Table91). This is a known issue and the workaround is to instantiate the IDELAY component with the DEFAULT delay set. Once the IDELAY is fully instantiated, then the timing analysis does match the data sheet. An alternate workaround could be to use IODELAY=BOTH constraint in the ucf.

This issue is only affects Virtex-5 devices.
AR# 38468
Date Created 10/13/2010
Last Updated 11/03/2010
Status Active
Type Known Issues
  • Virtex-5 FXT
  • Virtex-5 LX
  • Virtex-5 LXT
  • More
  • Virtex-5 SXT
  • Virtex-5 TXT
  • Virtex-5Q
  • Virtex-5QV
  • Less
  • ISE Design Suite - 12.1
  • ISE Design Suite - 12.2
  • ISE Design Suite - 12.3
  • ISE Design Suite - 13.1