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AR# 38476

12.3 EDK, MPMC - How do I create or debug a MPMC SDR SDRAM design?

Description


I am attempting to create an interface to a SDR SDRAM device using the MPMC.However, after adding the core to my design, initialization fails to complete.
How can I debug this issue?

Solution


The SDRAM PHY uses the Static PHY to access SDR SDRAM.
  • The MPMC datasheetcontains an in-depth section on static PHY functionality. A static PHY is required when using SDR SDRAM because the MIG PHY does not support SDR memory.
  • The SDRAM PHY generally requires a software calibration to be peformed before accessing memory. A software calibration example is provided in the MPMC driver examples folder. An example project utilizing this core and theMPMC memory test can bereferenced here:
    http://www.xilinx.com/txpatches/pub/applications/misc/ar38476.zip
  • The example C-code has been modified for debug visibility.A simulation version is also available, however, calibration might take on the order of 150ms of simulation time to calibrate.
  • After the final calibration value has been found, calibration can be fixed using the C_STATIC_PHY_RDEN_DELAY andC_STATIC_PHY_RDDATA_CLK_SEL parameters on the MPMC instance and the final DCM phase shift usingthe dcm_module instance C_PHASE_SHIFT parameter.By making theseparameters static and not running thecalibration software, less memory interface margin can be seen.
  • Simulation testbenches might require the DQ signals to be biased, in the above example, this is accomplished by PULLDOWN primitives.
  • The SDRAM PHY requires the addition of a timing constraint to the top-level UCF, typically named system.ucf:
    NET *rd_data_rise_rdclk MAXDELAY = 1000 ps;
  • Boards using the SDR SDRAM phy should strive to reduce trace skew between all SDRAM signals, as only a single read capture clock is adjusted during calibration, no per-bit deskew is performed.
  • One of themost commonly missed considerations is properly setting up the DCM phase adjustment control which helps to properly align the data with the memory clock.There is an example dcm_module demonstration in the data sheet and an additional clocking example demonstrated below:

    BEGIN mpmc
    PARAMETER INSTANCE = SDR_SDRAM_CUSTOM
    PARAMETER HW_VER = 4.03.a
    PARAMETER C_MEM_PARTNO = MT48LC16M16A2-75
    PARAMETER C_MEM_TYPE = SDRAM
    PARAMETER C_MEM_CE_WIDTH = 1
    PARAMETER C_MEM_CS_N_WIDTH = 1
    PARAMETER C_MEM_CLK_WIDTH = 1
    PARAMETER C_MEM_NUM_RANKS = 1
    PARAMETER C_MEM_DATA_WIDTH = 16
    PARAMETER C_MPMC_CLK0_PERIOD_PS = 8000
    PARAMETER C_MPMC_BASEADDR = 0x90000000
    PARAMETER C_MPMC_HIGHADDR = 0x91FFFFFF
    BUS_INTERFACE SPLB0 = mb_plb
    PORT SDRAM_Addr = fpga_0_SDR_SDRAM_CUSTOM_SDRAM_Addr
    PORT SDRAM_BankAddr = fpga_0_SDR_SDRAM_CUSTOM_SDRAM_BankAddr
    PORT SDRAM_CAS_n = fpga_0_SDR_SDRAM_CUSTOM_SDRAM_CAS_n
    PORT SDRAM_RAS_n = fpga_0_SDR_SDRAM_CUSTOM_SDRAM_RAS_n
    PORT SDRAM_WE_n = fpga_0_SDR_SDRAM_CUSTOM_SDRAM_WE_n
    PORT SDRAM_CE = fpga_0_SDR_SDRAM_CUSTOM_SDRAM_CE
    PORT SDRAM_CS_n = fpga_0_SDR_SDRAM_CUSTOM_SDRAM_CS_n
    PORT SDRAM_DM = fpga_0_SDR_SDRAM_CUSTOM_SDRAM_DM
    PORT SDRAM_DQ = fpga_0_SDR_SDRAM_CUSTOM_SDRAM_DQ
    PORT MPMC_Clk0 = sys_clk_s
    PORT MPMC_Clk90 = SDR_SDRAM_CUSTOM_mpmc_clk_90_s
    PORT MPMC_Rst = sys_periph_reset
    PORT SDRAM_Clk = unused_net
    END

    BEGIN clock_generator
    PARAMETER INSTANCE = clock_generator_0
    PARAMETER HW_VER = 2.01.a
    PARAMETER C_EXT_RESET_HIGH = 1
    PARAMETER C_CLKIN_FREQ = 125000000
    PARAMETER C_CLKOUT0_FREQ = 125000000
    PARAMETER C_CLKOUT0_BUF = TRUE
    PARAMETER C_CLKOUT0_PHASE = 0
    PARAMETER C_CLKOUT0_GROUP = PLL0
    PARAMETER C_CLKOUT1_FREQ = 125000000
    PARAMETER C_CLKOUT1_BUF = TRUE
    PARAMETER C_CLKOUT1_PHASE = 90
    PARAMETER C_CLKOUT1_GROUP = PLL0
    PORT CLKOUT0 = sys_clk_s
    PORT CLKOUT1 = SDR_SDRAM_CUSTOM_mpmc_clk_90_s
    PORT CLKIN = dcm_clk_s
    PORT LOCKED = Dcm_all_locked
    PORT RST = dcm_module_0_LOCKED
    END

    BEGIN dcm_module
    PARAMETER INSTANCE = dcm_module_0
    PARAMETER HW_VER = 1.00.d
    PARAMETER C_CLKOUT_PHASE_SHIFT = FIXED
    PARAMETER C_CLK0_BUF = TRUE
    PARAMETER C_CLK180_BUF = TRUE
    PARAMETER C_PHASE_SHIFT =0
    PORT CLKIN = dcm_clk_s
    PORT CLK180 = fpga_0_SDR_SDRAM_CUSTOM_SDRAM_Clk
    PORT LOCKED = dcm_module_0_LOCKED
    PORT CLK0 = dcm_module_0_CLK0
    PORT CLKFB = dcm_module_0_CLK0
    END

In this example, clock generator is used to generate the memory clock, and the dcm_module is used to phase-shift the clock correctly.

Note that each FPGA family and clock frequencymight require different DCM settings in the MHS and calibration software, see the associated FPGA User Guide for DCM phase shift min/max values. In this case, there are 256 functional DCM phase shift taps, starting at 0:
#define MPMC_MIN_TAPS0
#define MPMC_MAX_TAPS255
AR# 38476
Date Created 12/20/2010
Last Updated 02/05/2013
Status Active
Type General Article
Tools
  • EDK - 12.1
  • EDK - 12.2
  • EDK - 12.3
IP
  • Multi-Port Memory Controller (MPMC)