Project Navigator is not adding -L secureip in the fdo file when trying to perform a behavioral simulation of Virtex-6 and Spartan-6 FPGA designs.
The following is added in the fdo file:
vsim -voptargs="+acc" -t 1ps -L xilinxcorelib_ver -L unisims_ver -lib work TBV_01 glbl
The -L securip switch should also be included in order to simulate instantiate Xilinx components that use smartmodels.
Without the switch, vsim will give an error similar to the following for instantiated Xilinx primitives using smartmodels:
# ** Error: (vsim-3033) C:/xilinx/12.3/ISE_DS/ISE/verilog/src/unisims/GTHE1_QUAD.v(1831): Instantiation of 'B_GTHE1_QUAD' failed. The design unit was not found.
To work around this issue, add "-L secureip" to the "Other" vsim command line options in the simulation properties.
This issue is resolved in ISE Design Suite 13.1.