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AR# 3852

3.1i NGD2VER/NGD2VHDL - Bus indexes are always declared in descending order within simulation netlist


Keywords: Big Endian, Little Endian, testbench, bus, ordering

Urgency: Standard

General Description:
The Xilinx Alliance 2.1 HDL netlisters, NGD2VHDL and NGD2VER, will write out bus indexing in Little Endian style. This means that buses will always be written out with the largest number bit being the MSB (Most Significant Bit) of the bus, regardless of how the bus name was originally coded. (Bus index style is not always reflected in the input EDIF or XNF netlist to M1; therefore, it is currently not possible to determine which bus indexing style was originally used in the HDL code.)

As it is most common to name buses with the largest bit number representing MSB, the simulation netlist is always written out in this manner.

If a Big Endian style (where the smallest number bit is declared as MSB) was used for bus naming and brought through the M1 tools, the simulation netlist will remain functionally correct. However, the testbench used for RTL simulation can no longer match the testbench used for timing simulation, because the bus indexing will appear reversed for the Big Endian declared buses.



This problem was fixed in the Xilinx Alliance/Foundation 3.1i release.

If you are using Alliance/Foundation 2.1i or earlier, see Resolutions 2 and 3 for possible work-arounds.


Because the XNF netlist is flat, it is difficult to extract the order of the buses. The same is true of some CAE vendors' EDIF netlists for an input design, whether schematic or synthesis.

As the NGD database has no way to determine the ordering, none of the netlists generated by the back-end netlisters have a way to extract the order of the busses. Therefore, Xilinx assembles the bus in the following form:

input/output [higher_number:lower_number] bus_name;

The primary problem is that testbenches passing stimulus or monitoring waveforms of buses as a whole should be aware of the default bus ordering. We suggest that the design always be coded using the largest bit number as MSB.

An example of this in VHDL is to always use the DOWNTO syntax when declaring a bus:


For Verilog, simply declare the largest bit number first in the bus index notation:

input [3:0] MY_BUS;

This will allow consistent bus-naming index styles between the RTL code and the netlist produced by NGD2VER/NGD2VHDL netlister.


If it is not possible to use the Little Endian bus-indexing convention for the original HDL code, then there are two options:

1. Separate the testbenches -- one for RTL and the other for timing simulation.
2. Create a function in the testbench to reverse the bit ordering of Big Endian style buses for the timing simulation so that they match the bus-ordering of the RTL simulation.
AR# 3852
Date 06/13/2002
Status Archive
Type ??????
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