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AR# 38552

Design Assistant for PCI Express - Reasons for trn_tdst_rdy_n Deasserting Indefinitely


Why might trn_tdst_rdy_n deassert indefinitely or for long periods of time?

Note: This Answer Record is a part of the Xilinx Solution Center for PCI Express(Xilinx Answer 34536).TheXilinx Solution Center for PCI Express is available to address all questions related to PCIe.Whether you are starting a new design with PCIe or troubleshooting a problem, use the Solution Center for PCIeto guide you to the right information.


The core uses the trn_tdst_rdy_n signal to let the user know that it is not ready for more data.There are instances where trn_tdst_rdy_n deasserts for long periods of time or indefinitely.

This signal deasserts once the internal block transmit buffers are full and it can accept no more packets from the user application. This normally happens when the link partner either stops returning flow control credit updates. When the link partner stops returning flow control updates the endpoint cannot send any more packets until more credits are released.

The link partner may stop returning credits due to some type of error condition, for example,make sure that the TLPs you generate are not malformed. If you're interfacing with a switch and it receives a malformed TLP, then the switch may not update it's flow control credits. This will eventually lead the core to stop sending packets due to flow control.

Revision History
07/29/2011 - Initial Release

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
36049 Design Assistant for PCI Express - TRN User Application Interface Questions N/A N/A
AR# 38552
Date Created 07/29/2011
Last Updated 12/15/2012
Status Active
Type General Article
  • Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )
  • Endpoint Block Plus Wrapper for PCI Express
  • Spartan-6 FPGA Integrated Endpoint Block for PCI Express ( PCIe )