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AR# 38568

MIG v3.3-3.61 Virtex-6 DDR2/DDR3 - CK[0] and CK#[0] do not have to be placed at CC pins

Description

The clocking structure of the MIG design for Virtex-6 FPGA has changed in MIG v3.3, as an internally generated clock separate from CK is not used.

The MIG Virtex-6 DDR2/DDR3 design uses an internally generated clock to capture the data on DQ during reads and for resynchronization.

Previous versions used the CK generated clock to perform this.

Capturing data with an internally generated clock is beneficial because it is a true free-running clock and has no pre-/post-amble glitches as the DQS does.

For this reason, CK[0] and CK#[0] no longer use the CLKPERF dedicated path from the MMCM, and no are longer required to be placed at a CC pins. 

Solution

This is fixed in the ISE 13.1 MIG v3.7 software release.

In the meantime, you can ignore any UCF Verifier error messages that might occur.

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
38951 MIG v3.61 - Release Notes and Known Issues for ISE Design Suite 12.4-14.2 N/A N/A
AR# 38568
Date Created 10/25/2010
Last Updated 08/18/2014
Status Active
Type General Article
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
IP
  • MIG