The clocking structure of the MIG design for Virtex-6 FPGA has changed, starting with MIG v3.3, as an internally generated clock separate from CK is not used.
The MIG Virtex-6 DDR2/DDR3 design uses an internally generated clock to capture the data on DQ during reads and for resynchronization, while previous versions used the CK generated clock to perform this. Capturing data with an internally generated clock is beneficial because it is a true free-running clock and has no pre-/post-amble glitches as does the DQS. For this reason, CK[0] and CK#[0] no longer use the CLKPERF dedicated path from the MMCM, and no are longer required to be placed at a CC pins.