In the Virtex-6 FPGA MIG DDR3 core v3.5-91, when you select the SIM_BYPASS_INIT_CAL = "FAST" parameter, it speeds up the simulation of the Example Design and it calibrates error free.
When you select he SIM_BYPASS_INIT_CAL = "SKIP" parameter, you get an error in the tools and simulation stops.
When you select the SIM_BYPASS_INIT_CAL = "SKIP" parameter, bit alignment errors can occur in the PHY. Consequently, the data valid signal is then incorrectly asserted with a latency of one clock cycle. This is currently scheduled to be fixed in the 14.2 release, but until then make sure that you set the SIM_BYPASS_INIT_CAL parameter to "FAST".