^

AR# 38847 Virtex-6 Integrated Block Wrapper v1.6 for PCI Express - PIO_EP.vhd Does not Connect trn_trem_n to core

On line 292 in the PIO_EP.vhd file, it has this:

trn_trem_n => trn_trem_n_int,

The signal, trn_trem_n_int, is defined but not connected. This will cause improperly formed packets to be transmitted to the core resulting in malformed TLPs.


To fix this issue modify this line to read:

trn_trem_n => trn_trem_n,

The signal, trn_trem_n, is defined as an output port and is connected to the core.

Revision History
11/02/2010 - Initial Release
AR# 38847
Date Created 11/17/2010
Last Updated 12/17/2010
Status Active
Type
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
IP
  • Virtex-6 FPGA Integrated Endpoint Block for PCI Express
Feed Back