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AR# 38851

SPI-3 Link Layer v7.2 - Example design simulation testbench monitoring logic not connected


In v7.2 of the SPI-3 Link Layer core, the monitoring logic is not connected up in the simulation testbench. The monitoring logic checks that the data input to the rx interface matches the loopedback tx data available at the output. This affects all supported device families.


This issue has been fixed in v7.2rev1 of the core available as a patch for download; see (Xilinx Answer 35141).

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
35141 SPI-3 Link Layer v7.2 - Release Notes and Known Issues for ISE Design Suite 12.1 N/A N/A
AR# 38851
Date Created 11/05/2010
Last Updated 05/23/2014
Status Archive
Type General Article
  • SPI-3 Link Layer Interface, Multi-channel