UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 38853

12.1 EDK - My PCIe design on the ML506 board does not meet timing

Description

What can I do when my PCIe design on the ML506 board does not meeting timing?

Solution

The PCIe core comes with a recommendation that the -xe map and par switch be used. To enable this switch:

1. Open your project in XPS
2. Select the Project tab
3. Double click on the fast_runtime.opt file
4. Add the -xe switch under the option for Mapper and Place and Route.
5. Save and close the fast_runtime.opt file
6. Re-run your EDK design

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
34609 12.x EDK - Master Answer Record List N/A N/A
AR# 38853
Date Created 11/01/2010
Last Updated 12/15/2012
Status Active
Type General Article