To work around this issue, in the generated core's source directory edit the file with the same name as the generated coreandmake following modification. For example, if the CORE Generator default name is used, the file would be called s6_pcie_v2_3.v.
parameter [2:0] PM_CAP_AUXCURRENT= 3'd0
parameter PM_CAP_AUXCURRENT = 0
These warnings do not occur when using XST or Synplify with a VHDL design.
01/18/2012 - Updated; added reference to 45072
07/06/2011 - Initial Release
Note: "Version Found" refers to the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.